New Multilevel and Hierarchical Algorithms for Layout Density Control

Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing (CMP) which has varying e ects on device and interconnect features, depending on local layout characteristics. To reduce manufacturing variation due to CMP and to improve yield and performance predictability, the layout needs to be made uniform with respect to certain density criteria, by inserting \ ll" geometries into the layout. This paper presents an efcient multilevel approach to density analysis that a ords user-tunable accuracy. We also develop exact ll synthesis solutions based on combining multilevel analysis with a linear programming approach. Our methods apply to both at and hierarchical designs.